M166 Datasheet, PDF (65/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Instruction Description
DIVLU
32-by-16 Unsigned Division
DIVLU
Syntax
Operation
Data Types
Description
DIVLU op1
(MDL) ← (MD) / (op1)
(MDH) ← (MD) mod (op1)
WORD, DOUBLEWORD
Performs an extended unsigned 32-bit by 16-bit division of the two words
stored in the MD register by the source word operand op1. The unsigned
quotient is then stored in the low order word of the MD register (MDL) and
the remainder is stored in the high order word of the MD register ( MDH).
Condition Flags
E
Z
V
C
N
0
*
S
0
*
Addressing Modes
E Always cleared.
Z Set if result equals zero. Cleared otherwise.
V Set if an arithmetic overflow occurred, ie. the result cannot be repre-
sented in a word data type, or if the divisor (op1) was zero. Cleared
otherwise.
C Always cleared.
N Set if the most significant bit of the result is set. Cleared otherwise.
Mnemonic
DIVLU Rw_n
Format
7B nn
Bytes
2
Semiconductor Group
65
Version 1.2, 12.97