M166 Datasheet, PDF (125/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Instruction State Times
Instructions executed from the internal RAM require the same minimum time as if being fetched
from the internal ROM plus an instruction-length dependent number of state times, as follows:
For 2-byte instructions: T_Imin(RAM) = T_Imin(ROM) + 4 _* States
For 4-byte instructions: T_Imin(RAM) = T_Imin(ROM) + 6 _* States
In contrast to the internal ROM program execution, the minimum time T_Imin(ext) to process an
external instruction additionally depends on the instruction length. T_Imin(ext) is either 1 ALE Cycle
Time for most of the 2-byte instructions, or 2 ALE Cycle Times for most of the 4-byte instructions.
The following formula represents the minimum execution time of instructions fetched from an
external memory via a 16-bit wide data bus:
For 2-byte instructions: T_Imin(ext) = 1_*ACT + (T_Imin(ROM) - 2) _* States
For 4-byte instructions: T_Imin(ext) = 2_*ACTs + (T_Imin(ROM) - 2) _* States
Note: For instructions fetched from an external memory via an 8-bit wide data bus, the minimum
number of required ALE Cycle Times is twice the number for a 16-bit wide bus.
Additional State Times
Some operand accesses can extend the execution time of an instruction T_In. Since the additional
time T_Iadd is mostly caused by internal instruction pipelining, it often will be possible to evade these
timing effects in time-critical program modules by means of a suitable rearrangement of the
corresponding instruction sequences. Simulators and emulators offer a lot of facilities, which
support the user in optimizing his program whenever required.
• Internal ROM operand reads: T_Iadd = 2 _* States
Both byte and word operand reads always require 2 additional state times.
• Internal RAM operand reads via indirect addressing modes: T_Iadd = 0 or 1 _* State
Reading a GPR or any other directly addressed operand within the internal RAM space does NOT
cause additional state times. However, reading an indirectly addressed internal RAM operand will
extend the processing time by 1 state time, if the preceding instruction auto-increments or auto-
decrements a GPR as shown in the following example:
In
: MOV R1 , [R0+]
; auto-increment R0
In+1
: MOV [R3], [R2]
; if R2 points into the internal RAM space:
; TIadd = 1 _* State
In this case, the additional time can simply be avoided by putting another suitable instruction before
the instruction I_n+1 indirectly reading the internal RAM.
Semiconductor Group
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Version 1.2, 12.97