M166 Datasheet, PDF (117/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Addressing Modes
Rw, Rb:
Specifies direct access to any GPR in the currently active context (register bank). Both
’Rw’ and ’Rb’ require four bits in the instruction format. The base address of the current
register bank is determined by the content of register CP. ’Rw’ specifies a 4-bit word
GPR address relative to the base address (CP), while ’Rb’ specifies a 4 bit byte GPR
address relative to the base address (CP).
reg:
Specifies direct access to any (E)SFR or GPR in the currently active context (register
bank). ’reg’ requires eight bits in the instruction format. Short ’reg’ addresses from 00_H to
EF_H always specify (E)SFRs. In that case, the factor ’∆’ equates 2 and the base address
is 00’FE00_H for the standard SFR area or 00’F000_H for the extended ESFR area. ‘reg’
accesses to the ESFR area require a preceding EXT*R instruction to switch the base
address (not available in the SAB 8XC166(W) devices). Depending on the opcode of an
instruction, either the total word (for word operations) or the low byte (for byte opera-
tions) of an SFR can be addressed via 'reg'. Note that the high byte of an SFR cannot
be accessed via the 'reg' addressing mode. Short 'reg' addresses from F0_H to FF_H
always specify GPRs. In that case, only the lower four bits of 'reg' are significant for
physical address generation, and thus it can be regarded as being identical to the
address generation described for the 'Rb' and 'Rw' addressing modes.
bitoff:
Specifies direct access to any word in the bit-addressable memory space. 'bitoff'
requires eight bits in the instruction format. Depending on the specified 'bitoff' range, dif-
ferent base addresses are used to generate physical addresses: Short 'bitoff' addresses
from 00_H to 7F_H use 00’FD00_H as a base address, and thus they specify the 128 high-
est internal RAM word locations (00’FD00_Hh to 00’FDFE_H). Short 'bitoff' addresses from
80_H to EF_H use 00’FF00_H as a base address to specify the highest internal SFR word
locations (00’FF00_H to 00’FFDE_H) or use 00’F100_H as a base address to specify the
highest internal ESFR word locations (00’F100_H to 00’F1DE_H). ‘bitoff’ accesses to the
ESFR area require a preceding EXT*R instruction to switch the base address (not avail-
able in the SAB 8XC166(W) devices). For short 'bitoff' addresses from F0_H to FF_H, only
the lowest four bits and the contents of the CP register are used to generate the physi-
cal address of the selected word GPR.
bitaddr: Any bit address is specified by a word address within the bit-addressable memory
space (see 'bitoff'), and by a bit position ('bitpos') within that word. Thus, 'bitaddr'
requires twelve bits in the instruction format.
Semiconductor Group
117
Version 1.2, 12.97