M166 Datasheet, PDF (121/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Addressing Modes
Constants
The C166 Family instruction set also supports the use of wordwide or bytewide immediate
constants. For an optimum utilization of the available code storage, these constants are
represented in the instruction formats by either 3, 4, 8 or 16 bits. Thus, short constants are always
zero-extended while long constants are truncated if necessary to match the data format required for
the particular operation (see table below):
Mnemonic
#data3
#data4
#data8
#data16
#mask
Word Operation
0000_H + data3
0000_H + data4
0000_H + data8
data16
0000_H + mask
Byte Operation
00_H + data3
00_H + data4
data8
data16 ∧ FF_H
mask
Note: Immediate constants are always signified by a leading number sign ’#’.
Instruction Range (#irang2)
The effect of the ATOMIC and EXTended instructions can be defined for the following 1...4
instructions. This instruction range (1...4) is coded in the 2-bit constant #irang2 and is represented
by the values 0...3.
Branch Target Addressing Modes
Different addressing modes are provided to specify the target address and segment of jump or call
instructions. Relative, absolute and indirect modes can be used to update the Instruction Pointer
register (IP), while the Code Segment Pointer register (CSP) can only be updated with an absolute
value. A special mode is provided to address the interrupt and trap jump vector table, which resides
in the lowest portion of code segment 0.
Mnemonic Target Address
caddr
(IP) = caddr
rel
(IP) = (IP) + 2*rel
(IP) = (IP) + 2*(rel+1)
[Rw]
(IP) = ((CP) + 2*Rw)
seg
-
#trap7
(IP) = 0000_H + 4*trap7
Target Segment
-
-
-
-
(CSP) = seg
(CSP) = 0000_H
Valid Address Range
caddr
rel
rel
Rw
= 0000_H...FFFE_H
= 00_H...7F_H
= 80_H...FF_H
= 0...15
seg = 0...255(3)
trap7 = 00_H...7F_H
Semiconductor Group
121
Version 1.2, 12.97