M166 Datasheet, PDF (21/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Instruction Opcodes
4 Instruction Opcodes
The following pages list the instructions of the 16-bit microcontrollers ordered by their hexadecimal
opcodes. This helps to identify specific instructions when reading executable code, ie. during the
debugging phase.
Notes for Opcode Lists
1) These instructions are encoded by means of additional bits in the operand field of the
instruction
x0_H – x7_H:
Rw, #data3
or
x8_H – xB_H:
Rw, [Rw]
or
xC_H – xF_H: Rw, [Rw +]
or
Rb, #data3
Rb, [Rw]
Rb, [Rw +]
For these instructions only the lowest four GPRs, R0 to R3, can be used as indirect address
pointers.
2) These instructions are encoded by means of additional bits in the operand field of the
instruction
00xx.xxxx_B: EXTS
or
01xx.xxxx_B: EXTP
10xx.xxxx_B: EXTSR
or
11xx.xxxx_B: EXTPR
ATOMIC
EXTR
The ATOMIC and EXTended instructions are not available in the SAB 8XC166(W) devices.
Notes on the JMPR Instructions
The condition code to be tested for the JMPR instructions is specified by the opcode.
Two mnemonic representation alternatives exist for some of the condition codes.
Notes on the BCLR and BSET Instructions
The position of the bit to be set or to be cleared is specified by the opcode. The operand
‘bitoff.n’ (n = 0 to 15) refers to a particular bit within a bit-addressable word.
Notes on the Undefined Opcodes
A hardware trap occurs when one of the undefined opcodes signified by ‘----’ is decoded by
the CPU.
Semiconductor Group
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Version 1.2, 12.97