M166 Datasheet, PDF (127/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

30Mar98@15:00h
C166 Family Instruction Set
Instruction State Times
• Jumps into the internal ROM space: T_Iadd = 0 or 2 _* States
The minimum time of 4 state times for standard jumps into the internal ROM space will be extended
by 2 additional state times, if the branch target instruction is a double word instruction at a non-
aligned double word location (xxx2_H, xxx6_H, xxxA_H, xxxE_H), as shown in the following example:
label
: ....
; any non-aligned double word instruction
....
In+1
: ....
: JMPA cc^_UC, label
: (eg. at location 0FFE_H)
; if a standard branch is taken:
: TIadd = 2 _* States (TIn = 6 _* States)
A cache jump, which normally requires just 2 state times, will be extended by 2 additional state
times, if both the cached jump target instruction and its successor instruction are non-aligned
double word instructions, as shown in the following example:
label
: ....
; any non-aligned double word instruction
: (eg. at location 12FA_H)
It+1
: ^....
; any non-aligned double word instruction
: (eg. at location 12FE_H)
In+1
:JMPR cc^_UC, label
; provided that a cache jump is taken:
: TIadd = 2 _* States (TIn = 4 _* States)
If required, these extra state times can be avoided by allocating double word jump target
instructions to aligned double word addresses (xxx0_H, xxx4_H, xxx8_H, xxxC_H).
• Testing Branch Conditions: T_Iadd = 0 or 1 _* States
Mostly, NO extra time is required for conditional branch instructions to decide whether a branch
condition is met or not. However, an additional state time is required, if the preceding instruction
writes to the PSW register, as shown in the following example:
In
In+1
: BSET USR0
:JMPR cc^_Z, label
; write to PSW
; test condition flag in PSW: TIadd = 1 _* State
In this case, the extra state time can simply be intercepted by putting another suitable instruction
before the conditional branch instruction.
Semiconductor Group
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