M166 Datasheet, PDF(122/127 Page) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

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M166 Datasheet, PDF (122/127 Pages) Siemens Semiconductor Group – C16x Family of Siemens 16-Bit CMOS Single-Chip Microcontrollers

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30Mar98@15:00h

C166 Family Instruction Set

Addressing Modes

caddr:

Specifies an absolute 16-bit code address within the current segment. Branches MAY

NOT be taken to odd code addresses. Therefore, the least significant bit of âcaddrâ must

always contain a â0â, otherwise a hardware trap would occur.

rel:

This mnemonic represents an 8-bit signed word offset address relative to the current

Instruction Pointer contents, which points to the instruction after the branch instruction.

Depending on the offset address range, either forward (ârelâ= 00H to 7FH) or backward

(ârelâ= 80H to FFH) branches are possible. The branch instruction itself is repeatedly exe-

cuted, when ârelâ = â-1â (FFH) for a word-sized branch instruction, or ârelâ = â-2â (FEH) for a

double-word-sized branch instruction.

[Rw]:

In this case, the 16-bit branch target instruction address is determined indirectly by the

content of a word GPR. In contrast to indirect data addresses, indirectly specified code

addresses are NOT calculated via additional pointer registers (eg. DPP registers).

Branches MAY NOT be taken to odd code addresses. Therefore, the least significant bit

of the address pointer GPR must always contain a â0â, otherwise a hardware trap would

occur.

seg:

Specifies an absolute code segment number. The devices of the SAB 80C166 group

support 4 different code segments, while the devices of the C167/5 group support 256

different code segments, so only the two or eight lower bits (respectively) of the âsegâ

operand value are used for updating the CSP register.

#trap7:

Specifies a particular interrupt or trap number for branching to the corresponding inter-

rupt or trap service routine via a jump vector table. Trap numbers from 00H to 7FH can

be specified, which allow to access any double word code location within the address

range 00â0000H...00â01FCH in code segment 0 (ie. the interrupt jump vector table).

For the association of trap numbers with the corresponding interrupt or trap sources

please refer to chapter âInterrupt and Trap Functionsâ.

Semiconductor Group

122

Version 1.2, 12.97

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