SM8521 Datasheet, PDF (48/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
UART Transmit Data Register (URTT)
Transmit data register URTT is an 8-bit write only
register which stores the UART transmit data.
When the transmission operation starts, the content
of this register LSB first is output from P71/TxD pin.
UART Receive Data Register (URTR)
Receive data register URTR is an 8-bit read only
register which stores the UART receive data.
When the receive operation starts, the receive data
LSB first will be moved into the receive data shift
register from P70/RxD pin. Once the receive
operation is complete, the content of the receive
data shift register is loaded into this receive data
register URTR (duplex buffer).
UART Status Register (URTS)
Status register (URTS) is an 8-bit read only register
containing the flags of the UART interface transmit/
receive status.
Bit 7
-
0
- RBSY OR FE PE TDRE TDRF
Bits 7 to 6 : Set ‘0’
Bit 5 : Receiver busy bit (RBSY)
BIT
CONTENT
0 UART receiver is other than the following.
1 UART receiver processing incoming data.
Bit 4 : Overrun error bit (OR)
BIT
CONTENT
Clear condition
0 (1) While reading the status register URTS
(2) Hardware reset
Set condition
(1) While overrun error occurs (the next
1
receive is complete under the bit RDRF
= ‘1’. ) at receive data
Bit 3 : Frame error bit (FE)
BIT
CONTENT
Clear condition
0 (1) While reading the status register URTS
(2) Hardware reset
Set condition
1 (1) While frame error occurs (stop bit = ‘0’
is detected.) at receive data.
Bit 2 : Parity error bit (PE)
BIT
CONTENT
Clear condition
0 (1) While reading the status register URTS
(2) Hardware reset
Set condition
1
(1) Parity error occurs at receive data
Bit 1 : Transmit data register empty bit (TDRE)
BIT
CONTENT
Clear condition
0 (1) While writing to transmit data register
URTT
Set condition
(1) While having finished transmitting
1
operation.
(2) Hardware reset
Bit 0 : Receiver data register full bit (RDRF)
BIT
CONTENT
Clear condition
(1) While reading from receive data register
0
URTR
(2) Hardware reset
Set condition
(1) While receive data is transferring to
1
receive data register URTR from receive
data shift register.
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