SM8521 Datasheet, PDF (13/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
Address Space
The SM85CPU has a 64 k-byte address space,
which is divided into RAM (0000H-0FFFH) and ROM
(1000H-FFFFH) areas. The address 0000H-007FH
are both shared by RAM and register file. Fig. 9-1
shows the SM8521 Memory Map.
The RAM and register file allocated at 0000H-007FH
can be selected by the addressing mode
designated by instructions.
The SM8521 supports an Memory Management
Unit used to external memory area expantion.
Refer to "Memory Management Unit (MMU)".
ROM Area
ROM area starts at the address 1000H of the space
address. The first portion (1000H-101FH) is reserved
for the interrupt vector table. Each 2 bytes entry in
the vector table contains the address of interrupts.
When an interrupt encountered, the CPU jumps to
the corresponding branch address of vector table
for program executing. The address 1020H marks
the start of the user program area itself. Executing
always starts at 1020H after hardware reset.
Register File Area
The register file is allocated between 0000H and
007FH. The first 16 bytes (0000H-000FH) area are
general registers. The remainder is for CPU control
registers, peripherals control register and data
register.
RAM Area
The RAM area starts at the beginning 0000H of the
address space. It overlaps the register file for the
address 0000H-007FH.
This arrangement is to shorten the instruction
length as much as possible and to permit the use
with both RAM and the register file for faster
execution.
Data
Type
Bit
Byte
Word
Register file address
0000H-00FFH
0000H-00FFH
Even byte, 0000H-00FEH,
following byte (odd byte)
Memory address
0000H-00FFH or FF00H-FFFFH
0000H-00FFH
0000H-00FFH or FF00H-FFFFH
(Under shorthand)
0000H-FFFEH
following byte
7
76
MSB
MSB
Data Format
5432
Upper 8-bit
Lower 8-bit
Address
Low
0
10
LSB
LSB
BCD
0000H-00FFH
0000H-00FFH
Upper BCD digit
Lower BCD digit
High
Fig. 3 Register File/Memory Data Formats
- 13 -