SM8521 Datasheet, PDF (19/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
System clock frequency control
Main-clock
fCK
1/2
fCK/2
1/2 1/2 1/2 1/2
CG
fCK/2 fCK/4 fCK/8 fCK/16 fCK/32
5
f32K
System clock fSYS
Prescaler PRS0 (frequency divider on fCK/2)
1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
fc10 fc11 fc12 fc13 fc14 fc15 fc16
Prescaler PRS2 (frequency divider on fc10)
1/2 1/2 1/2 1/2 1/2
fc12 fc13 fc14 fc15
For warming
up counter
Warming up counter (frequency divider on fc10)
1/2 1/2 1/2 1/2 1/2 1/2 1/2
f32K
Sub-clock
Prescaler PRS1 (frequency divider on f32K)
1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
fx1 fx2 fx3 fx4 fx5 fx6 fx7 fx8
8
To function blocks
8
Fig. 8 SM8521 Clock System (Equivalent Circuit for Clock System Peripheral Blocks)
Clock change register (CKKC)
Clock change register CKKC is an 8-bit readable/
writable register containing the control of system
clock change and the setting of warming up period
after waking up from the STOP mode.
Clock change register CKKC is initialized to 00H
after hardware reset.
Bit 7
0
FCPUEN MCKSTP FCPUS2 FCPUS1 FCPUS0 TFCPU WUPS1 WUPS0
Bit 7 : Clock change enable bit (FCPUEN)
BIT
CONTENT
0 Disables system clock speed change
1 Enables system clock speed change
Bit 6 : Main-clock stopped bit (MCKSTP)
Main-clock stopped allows switching to sub-clock
used as system clock.
BIT
CONTENT
0 Main-clock operation
1 Main-clock stop
Bits 5 to 3 : System clock selection bits
(FCPUS2-FCPUS0)
Under the bit FCPUEN = ‘1’, if executes the
STOP instruction, the bits will be valid.
BIT
SYSTEM CLOCK FREQUENCY
000 System clock = (1/32) x main-clock
001 System clock = (1/16) x main-clock
010 System clock = (1/8) x main-clock
011 System clock = (1/4) x main-clock
100 System clock = (1/2) x main-clock
101, 110 Reserved
111 System clock = (1/2) x sub-clock
Bit 2 : Reserved bit (TFCPU)
Always write ‘0’ to this position. Writing a ‘1’
produces unrealiable operation.
Bits 1 to 0 : Warming up selection bits
(WUPS1-WUPS10)
The bits are able to set the warming up period
of after wake up from STOP mode.
WARMING UP PERIOD AFTER STOP
BIT MODE RELEASES
(when main-clock (fCK) = 10 MHz)
00 2¹⁸ x main-clock period (26.21 ms)
01 2¹⁷ x main-clock period (13.10 ms)
10 2¹⁶ x main-clock period (6.553 ms)
11 2¹⁵ x main-clock period (3.276 ms)
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