SM8521 Datasheet, PDF (11/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
CPU CONTROL REGISTER
The SM85CPU has the following control register :
processor status PS0, processor status PS1,
system configuration register SYS, stack pointer
SPH, SPL and program counter PC. All control
register except the program counter PC are
members of the register file and accessible by the
register file R and the register file pair RR
addressing modes.
Processor status 0 (PS0)
The processor status PS0 is an 8-bit readable/
writable register containing 2 fields, the upper 5-bit
is register pointer (RP) and the lower 3-bit is
interrupt mask.
Bit 7
0
PR4 PR3 PR2 PR1 PR0 IM2 IM1 IM0
Bits 7 to 3 : Register pointer (RP)
This gives, in 8 bytes unit, the starting address
in RAM for general purpose registers.
Bits 2 to 0 : Interrupt mask bits (IM)
BIT
CONTENT
000
All maskable interrupts recognized
001
010 Maskable interrupts with level 1 to 12 recognized
011 Maskable interrupts with level 1 to 10 recognized
100 Maskable interrupts with level 1 to 8 recognized
101 Maskable interrupts with level 1 to 6 recognized
111 Maskable interrupts with level 1 tto 4 recognized
111 Maskable interrupts with level 1 to 2 recognized
PS0
RP
IM
Address
Low
R0
R1
R14
R15
Ex.) If RP = 00000B, general purpose
registers will be virtually allocated
at internal RAM 0000H-000FH.
If RP = 00001B, general purpose
registers will be virtually allocated
at internal RAM 0008H-0017H.
Internal RAM
High
Fig. 2 Register Pointer (RP) Setting Example
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