SM8521 Datasheet, PDF (38/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

LCV (Display vertical timing register)
Bit 7
0
VBLNK - VL1 VL0 VBWD3 VBWD2 VBWD1 VBWD0
Bit 7 : V-blank bit (read only)
BIT
STATUS
0 Non-vertical blank period
1 Vertical blank period
Bit 6 : Sets ‘0’.
Bits 5 to 4 : V-line size bits
BIT
VERTICAL LINE SIZE
00 100
01 160
10 200
Bits 4 to 0 : V-blank width bits
NOTE :
V-blank width bit must not be filled with 0000B. Otherwise,
LCDC interrupt can not be effective.
Horizontal display cycle = (shift clock x LCDC/DMA
clock ) x (H-timing + 1)
Shift clock = 40 (at H-dot size = 160),
50 (at H-dot size = 200)
Frame cycle = Horizontal display cycle x (V-line
size + V-blank width)
SM8521
DMC (DMA control register)
Bit 7
0
DMST - - INDCY INDCX TRN1 TRN0 COOVr
Bit 7 : DMA start bit
BIT
STATUS
0 DMA stops
1 DMA starts transfering data
Bits 6 to 5 : Set ‘0’.
Bit 4 : Increment y/decrement y bit
(Increment/decrement y-coordinate of source)
BIT
STATUS
0 Increment y
1 Decrement y
Bit 3 : Increment x/decrement x bit
(Increment/decrement x-coordinate of source)
BIT
STATUS
0 Increment x
1 Decrement x
Bits 2 to 1 : Transfer mode bits
BIT
SOURCE→DESTINATION
00 VRAM→VRAM
01 ROM→VRAM
10 Extend RAM→VRAM
11 VRAM→Extend RAM
Bit 0 : Compound/overwrite bit
BIT
STATUS
0 Compound mode
1 Overwrite mode
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