SM8521 Datasheet, PDF (37/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
Registers
LCDC/DMA registers are shown below. LCDC
register is initialized at the system initialization. After
setting each parameter, set the DMA start bit to ‘1’
and execute HALT instruction, then DMA transfer
starts.
LCC (LCD control/status register)
Bit 7
0
DISON DISPG GRAD1 GRAD0 LCCL2 LCCL1 LCCL0 NORWH
Bit 7 : Display ON/OFF
BIT
DISPLAY ON/OFF
0 Display OFF
1 Display ON
Bit 6 : Display page A/B bit
BIT
DISPLAY PAGE
0 Page A
1 Page B
Bits 5 to 4 : Gradation control bits
(Depth of black and white on real LCD)
BIT
GRADATION CHOOSEN
00 0 Black 1 Gray 1 2 Gray 2 3 White
01 0 Black 1 Gray 1 2 Gray 3 3 White
10
Reserved
11 0 Black 1 Gray 2 2 Gray 3 3 White
NOTE : Gray scale
White Gray3 Gray2 Gray1 Black
Bits 3 to 1 : LCDC/DMA clock bits
BIT
LCDC/DMA CLOCK
000 fCK/2
001 fCK/4
010 fCK/6
011 fCK/8
100 fCK/10
101 fCK/12
110 fCK/14
111 fCK/16
Bit 0 : Normal white bar bit
BIT
STATUS
0 Normal white
1 Normal black
LCH (Display horizontal timing register)
Bit 7
0
- - HD0T HTIM4 HTIM3 HTIM2 HTIM1 HTIM0
Bits 7 to 6 : Set ‘0’.
Bit 5 : H-dot size bit
BIT
HORIZONTAL DOT SIZE
0 160
1 200
Bits 4 to 0 : H-timing bits
NOTE :
V-blank width bit must not be filled with 0000B. Otherwise,
LCDC interrupt can not be effective.
Horizontal display cycle = (shift clock x LCDC/DMA
clock ) x (H-timing + 1)
Shift clock = 40 (at H-dot size = 160),
50 (at H-dot size = 200)
Frame cycle = Horizontal display cycle x (V-line
size + V-blank width)
- 37 -