SM8521 Datasheet, PDF (43/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

In order of Low and High, each 4-bit data is
specified. Each SG0 and SG1 waveform register
stores 4-bit x 32-step data as shown below.
Refer to SG0 and SG1 waveform registers in Fig.
9-3.
The most significant bit of each 4-bit data indicates
SM8521
positive and negative.
That means, range of each 4-bit data is –8 to +7.
NOTE :
Waveform register read/write is possible only when SG is
disable.
D/A output level
+5.0 V
7
43
0
0
STEP1
STEP0
1
STEP3
STEP2
2
STEP5
STEP4
3
STEP7
STEP6
4
STEP9
STEP8
5
STEP11
STEP10
6
STEP13
STEP12
7
STEP15
STEP14
8
STEP17
STEP16
9
STEP19
STEP18
A
STEP21
STEP20
B
STEP23
STEP22
C
STEP25
STEP24
D
STEP27
STEP26
E
STEP29
STEP28
F
STEP31
STEP30
Fig. 20 Sound Waveform Register
+2.5 V
Rump-up period
NOTES :
• Mute level of the D/A should be created by software.
• Attenuate not to exceed capacity of D/A output level (0-5 V) by software.
• To avoid pop-noise, make rump-up and down period by software.
Fig. 21 Example of D/A Output
Rump-down period
Time
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