SM8521 Datasheet, PDF (15/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
Bus Timing
The SM85CPU is variable for system clock. The bit
FCPUS2-FCPUS0 (bits 5 to 3 : CKKC) of the clock
changing register CKKC can select system clock to
1/2, 1/4, 1/8, 1/16 and 1/32 of the main clock and
1/2 of sub-clock. The CPU operates at 1/32 clock
of the main clock after hardware reset.
INTERNAL MEMORY ACCESS TIMING
The read cycle of internal RAM is 2 cycles. The
internal RAM supports 2 cycles for reading or
writing.
EXTERNAL MEMORY ACCESS TIMING
The external memory supports 2 cycles for reading
or writing. Fig. 5 shows the read timing and Fig. 6
shows the write timing.
INSTRUCTION PREFETCH
The SM85CPU, which execution cycle overlaps
with the OP code, fetches next instruction OP
code during one instruction execution cycle. For
example, the execution time for 2 bytes instructions
(MOV R, r) of transferring the RAM contents to a
register is 4 cycles.
Internal clock
Pre-instruction
Transfer
instruction
Next instruction
Executing
preinstruction
OP code
fetch
Operand
fetch
RAM
read
Register
write
Fetch cycle
OP code
fetch
Execution
cycle
Execution time
Fig. 4 Instruction Execution for Transfer Instruction (2 Bytes)
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