SM8521 Datasheet, PDF (40/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

DMPL (Pallet register)
DMPL register specifies gradation to dot data.
When transferring, gradation data concerned with
dot data of the DMPL register is stored to VRAM.
Bit 7
0
COL31COL30 COL21 COL20 COL11 COL10 COL01 COL00
Bits 7 to 6 : Dot data color 0
Bits 5 to 4 : Dot data color 1
Bits 3 to 2 : Dot data color 2
Bits 1 to 0 : Dot data color 3
ROM/VRAM
Dot data = color 2 (10B)
SM8521
Example :
When dot data color 2 (10B) is specified under the
status of the DMPL register filled with ∗∗01∗∗∗∗B,
bit 4 and 5 of the DMPL register are automatically
selected. Dot data changes from color 2 (10B) to
color 1 (01B). Then the dot data color 1 moves to
specified VRAM.
Color 3 Color 2 Color 1 Color 0
DMPL
01
VRAM
Dot data = color 1 (01B)
NOTE : Color 0-3 are not depth gradation. Depth of black and white on LCD is fixed by Gradiation control bit of the LCC register.
Fig. 18 How to Select Gradations
DMBR (ROM bank register)
DMBR register specifies ROM's bank being
transferred. (Organization of bank is 256 x 256
dots. Bank specifies external memory address
irrespective of MMU.)
Bit 7
0
- DMBR6 DMBR5 DMBR4 DMBR3 DMBR2 DMBR1 DMBR0
DMVP(DMVP register)
DMVP register specifies a page (VRAM) in case of
specifying VRAM to source and destination.
Bit 7
0
Bits 7 to 2 : Set ‘0’.
Bit 1 : Destination page A/B
BIT
CONTENT
0 Destination page A
1 Destination page B
Bit 0 : Source page A/B
BIT
CONTENT
0 Source page A
1 Source page B
- - - - - - SOUAB DESAB
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