SM8521 Datasheet, PDF (24/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
Table 3 SM8521 Interrupt Vectors Location and Their Priority
VECTOR LOCATION
INTERRUPT SOURCE
SYMBOL PRIORITY^∗
1000H
DMA
DMAINT
1
1002H
Timer 0
TIM0INT
2
1006H
External interrupt
EXTINT
3
1008H
UART transmit/receive complete
UARTINT
4
100EH
LCD controller
LCDCINT
5
1012H
Timer 1
TIM1INT
6
1016H
Clock
CKINT
7
101AH
Input/output port
PIOINT
8
101CH
Watchdog timer overflow
WDTINT
–
101EH
NMI, illegal instruction
NMIINT, ILLINT
–
∗ The priority levels determine the order in which the chip process simultaneous interrupts. It also denotes the priority level of
mask interrupts by setting the bits IM2-IM0 (bits 2-0 : PS0).
REGISTER EXPLANATIONS
PS0 (Interrupt maskbit (IM) of processor status 0)
The bits IM2-IM0 can set the acceptable level for
interrupt. The maskable interrupt requested by CPU
is set 1 to 8 priority levels. These bits IM2-IM0
determine processing interrupts which priority
levels.
Bits 2 to 0 : Interrupt mask bits (IM2-IM0)
BIT
CONTENT
000 All maskable interrupts recognized.
001 All maskable interrupts recognized.
Maskable interrupts with 1 to 7 level
010
recognized.
Maskable interrupts with 1 to 6 level
011
recognized.
Maskable interrupts with 1 to 5 level
100
recognized.
Maskable interrupts with 1 to 4 level
101
recognized.
Maskable interrupts with 1 to 3 level
110
recognized.
Maskable interrupts with 1 to 2 level
111
recognized.
NOTE :
When an interrupt enables by interrupt mask bit, if all
interrupt conditions are setup, then the CPU starts to the
interrupt processing.
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