SM8521 Datasheet, PDF (16/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

• External memory access timing (read timing)
SM8521
A0-A20
RDB
D0-D7
tRSA
tRSD
tWRD
Valid data
tRHA
tRHD
tRSA : The time between address firm and RDB signal
falling Low level firm.
tRSD : The time between RDB signal firm and input valid
data firm.
tWRD : RDB signal Low level width.
tRHA : The time between RDB signal rising High level firm
and address change.
tRHD : The time between RDB signal rising High level firm
and output data floating.
Load capacitance is 50 pF.
Fig. 5 External Memory Access Timing (Read Timing)
Operating condition
PARAMETER
SYMBOL
MIN.
Address setup time
tRSA
Read data setup time
tRSD
RDB signal pulse width
tWRD
Address hold time
tRHA
tSYS – 50
0
Read data hold time
tRHD
0
NOTE :
1. tSYS : The system clock period (main clock x 1/2) when the
low order 3 bits in the clock change register
FCPUS2-FCPUS0 are 100B.
TYP.
tSYS
(VDD = 4.5 to 5.5 V, TOPR = –10 to 60˚C)
MAX.
UNIT NOTE
tSYS + 50
ns
1
tSYS/2 – 30
ns
1
tSYS
ns
1
ns
ns
- 16 -