SM8521 Datasheet, PDF (17/56 Pages) Sharp Electrionic Components – 8-Bit Single-Chip Microcomputer

SM8521
• External memory access timing (write timing)
A0-A20
WRB
t_WSA
t_WWR
t_WHA
D₀-D7
Invalid data
t_WSD
Valid data
t_WHD
tWSA : The time between address firm and WRB signal
falling Low level firm.
tWSD : The time between WRB signal rising High level firm
and output valid data firm.
tWWR : WRB signal Low level width.
tWHA : The time between WRB signal rising High level firm
and address change.
tWHD : The time between WRB signal rising High level firm
and output data floating.
Load capacitance is 50 pF.
Fig. 6 External Memory Access Timing (Write Timing)
Operating condition
PARAMETER
SYMBOL
MIN.
Address setup time
tWSA
Data setup time
tWSD
tSYS – 50
WRB signal pulse width
tWWR
Address hold time
tWHA
tSYS – 60
10
Data hold time
tWHD
10
NOTE :
1. tSYS : The system clock period (main clock x 1/2) when the
low order 3 bits in the clock change register
FCPUS2-FCPUS0 are 100B.
(VDD = 4.5 to 5.5 V, TOPR = –10 to 60˚C)
TYP.
MAX.
UNIT NOTE
tSYS
tSYS + 50
ns
1
tSYS + 30
ns
1
tSYS
ns
1
ns
ns
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