K4T51043QE Datasheet, PDF (41/45 Pages) Samsung semiconductor – 512Mb E-die DDR2 SDRAM Specification

K4T51043QE
K4T51083QE
K4T51163QE
DDR2 SDRAM
20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for
a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input sig-
nal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for
a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
DQS
DQS
tDS tDH
tDS tDH
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF(dc)
V_IL(dc) max
V_IL(ac) max
V_SS
Figure 18 - Differential input waveform timing - tDS and tDH
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test. See Figure 19.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test. See Figure 19.
CK
CK
tIS tIH
tIS tIH
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF(dc)
V_IL(dc) max
V_IL(ac) max
V_SS
Figure 19 - Differential input waveform timing - tIS and tIH
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Rev. 1.8 July 2007