K4T51043QE Datasheet, PDF (23/45 Pages) Samsung semiconductor – 512Mb E-die DDR2 SDRAM Specification

K4T51043QE
K4T51083QE
K4T51163QE
DDR2 SDRAM
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS
through a 20 Ω to 10 kΩ resistor to insure proper operation.
DQS/
DQS
DQ
DM
DQS
t_DQSH
t_DQSL
DQS
t_WPRE
V_IH(ac)
VIH(dc)
D
D
D
V_IL(ac)
t_DS
V_IH(ac) ^tDS
V_IL(dc)
t_DH
DMin
DMin
DMin
V_IL(ac)
Figure 3 - Data Input (Write) Timing
t_WPST
D
t_DH
V_IH(dc)
DMin
V_IL(dc)
CK
CK/CK
CK
DQS/DQS
DQ
t_CH
t_CL
DQS
DQS
t_RPRE
t_DQSQmax
Q
t_QH
Q
Q
t_DQSQmax
Figure 4 - Data Output (Read) Timing
t_RPST
Q
t_QH
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to VSS.
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
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Rev. 1.8 July 2007