K4T51043QE Datasheet, PDF (2/45 Pages) Samsung semiconductor – 512Mb E-die DDR2 SDRAM Specification

K4T51043QE
K4T51083QE
K4T51163QE
Table of Contents
DDR2 SDRAM
1.0 Ordering Information ....................................................................................................................4
2.0 Key Features .................................................................................................................................4
3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5
3.1 x4 package pinout (Top View) : 60ball FBGA Package ........................................................................5
3.2 x8 package pinout (Top View) : 60ball FBGA Package .........................................................................6
3.3 x16 package pinout (Top View) : 84ball FBGA Package .......................................................................7
3.4 FBGA Package Dimension(x4/x8) .....................................................................................................8
3.5 FBGA Package Dimension(x16) .......................................................................................................9
4.0 Input/Output Functional Description ........................................................................................10
5.0 DDR2 SDRAM Addressing .........................................................................................................11
6.0 Absolute Maximum DC Ratings .................................................................................................12
7.0 AC & DC Operating Conditions .................................................................................................12
7.1 Recommended DC Operating Conditions (SSTL - 1.8) .......................................................................12
7.2 Operating Temperature Condition ..................................................................................................13
7.3 Input DC Logic Level ....................................................................................................................13
7.4 Input AC Logic Level ....................................................................................................................13
7.5 AC Input Test Conditions ..............................................................................................................13
7.6 Differential input AC logic Level .....................................................................................................14
7.7 Differential AC output parameters ..................................................................................................14
8.0 ODT DC electrical characteristics .............................................................................................14
9.0 OCD default characteristics ......................................................................................................15
10.0 IDD Specification Parameters and Test Conditions ..............................................................16
11.0 DDR2 SDRAM IDD Spec ...........................................................................................................18
12.0 Input/Output capacitance .........................................................................................................19
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................19
13.1 Refresh Parameters by Device Density ........................................................................................19
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................19
13.3 Timing Parameters by Speed Grade ............................................................................................20
14.0 General notes, which may apply for all AC parameters ........................................................22
15.0 Specific Notes for dedicated AC parameters ..........................................................................23
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Rev. 1.8 July 2007