K4T51043QE Datasheet, PDF (20/45 Pages) Samsung semiconductor – 512Mb E-die DDR2 SDRAM Specification

K4T51043QE
K4T51083QE
K4T51163QE
DDR2 SDRAM
13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Symbol
tAC
tDQSCK
tCH
tCL
DDR2-800
min
max
- 400
400
- 350
350
0.45
0.55
0.45
0.55
DDR2-667
min
max
-450
+450
-400
+400
0.45
0.55
0.45
0.55
DDR2-533
min
max
-500
+500
-450
+450
0.45
0.55
0.45
0.55
DDR2-400
min
max
-600
+600
-500
+500
0.45
0.55
0.45
0.55
Units Notes
ps
ps
tCK
tCK
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
tHP
min(tCL,t
CH)
tCK
2500
tDH(base) 125
x
8000
x
min(tCL,
tCH)
3000
175
x
8000
x
min(tCL,
tCH)
3750
225
x
8000
x
min(tCL,
tCH)
5000
275
DQ and DM input setup time
tDS(base)
50
x
100
x
100
x
150
Control & Address input pulse width for each input tIPW
DQ and DM input pulse width for each input
tDIPW
0.6
x
0.35
x
0.6
x
0.35
x
0.6
x
0.6
0.35
x
0.35
x
8000
x
x
x
x
ps 20,21
ps
24
ps
15,16,
17,20
ps
15,16,
17,21
tCK
tCK
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tHZ
x
tAC max
x
tAC max
x
tAC max
x
tAC max ps
tLZ(DQS) tAC min tAC max tAC min tAC max tAC min tAC max tAC min tAC max ps
27
tLZ(DQ)
2* tAC
min
tAC max
2*tAC
min
tAC max 2* tACmin tAC max 2* tACmin tAC max
ps
27
DQS-DQ skew for
nals
DQS and associated DQ sig-
tDQSQ
DQ hold skew factor
tQHS
DQ/DQS output hold time from DQS
tQH
x
200
x
x
300
x
tHP -
tQHS
x
tHP -
tQHS
240
x
300
x
350
ps
22
340
x
400
x
450
ps
21
x
tHP -
tQHS
x
tHP -
tQHS
x
ps
First DQS
edge
latching
transition
to
associated clock
tDQSS
DQS input high pulse width
tDQSH
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
tDQSL
0.35
tDSS
0.2
tDSH
0.2
x
0.35
x
0.2
x
0.2
x
0.35
x
0.2
x
0.2
x
0.35
x
0.2
x
0.2
x
tCK
x
tCK
x
tCK
Mode register set command cycle time
Write postamble
Write preamble
tMRD
tWPST
tWPRE
2
x
2
x
0.4
0.6
0.4
0.6
0.35
x
0.35
x
2
x
0.4
0.6
0.35
x
2
0.4
0.35
x
tCK
0.6
tCK 19
x
tCK
Address and control input hold time
Address and control input setup time
Read preamble
tIH(base)
250
x
275
x
375
x
475
x
ps
14,16,
18,23
tIS(base)
175
x
200
x
250
x
350
x
ps
14,16,
18,22
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK 28
Read postamble
tRPST
Active to active
size products
command
period
for
1KB
page
tRRD
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK 28
7.5
x
7.5
x
7.5
x
7.5
x
ns
12
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Rev. 1.8 July 2007