M37517F8HP Datasheet, PDF (94/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
MULTI-MASTER I²C-BUS BUS LINE CHARACTERISTICS
Table 33 Multi-master I²C-BUS bus line characteristics
Symbol
Parameter
Test ^{Standard clock mode} High-speed clock mode
conditions _Min.
Max.
Min.
Max.
Unit
tBUF
Bus free time
4.7
1.3
µs
tHD;STA
Hold time for START condition
4.0
0.6
µs
tLOW
Hold time for SCL clock = “0”
4.7
1.3
µs
tR
Rising time of both SCL and SDA signals
1000 ^{20+0.1Cb (Note)} 300
ns
tHD;DAT
tHIGH
Data hold time
Hold time for SCL clock = “1”
Fig. 86
0
4.0
0
0.9
µs
0.6
µs
tF
Falling time of both SCL and SDA signals
300 ^{20+0.1Cb (Note)} 300
ns
tSU;DAT
Data setup time
250
100
ns
tSU;STA
Setup time for repeated START condition
4.7
0.6
µs
tSU;STO
Setup time for STOP condition
4.0
0.6
µs
Note: Cb = total capacitance of 1 bus line
SDA
tBUF
tLOW
tR
tF
SCL ^P
S
tHD:STA
Sr
tsu:STO
P
tHD:STA
tHD:DTA
tHIGH
tsu:DAT
tsu:STA
Fig. 86 Timing diagram of multi-master I²C-BUS
S: START condition
Sr: RESTART condition
P: STOP condition
Measurement output pin
100pF
CMOS output
Fig. 87 Circuit for measuring output switching characteristics
Rev.1.01 Aug 02, 2004 page 94 of 96