M37517F8HP Datasheet, PDF (32/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
(1)7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I²C control register (address 002E16) to “0”. The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I²C address register
(address 002C16). At the time of this comparison, address com-
parison of the RWB bit of the I²C address register (address
002C16) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 36,
(1) and (2).
(2)10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I²C control register (address 002E16) to “1”. An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I²C address register (address 002C16). At the time of this
comparison, an address comparison between the RWB bit of
the I²C address register (address 002C16) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is pro-
cessed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I²C status register (address 002D16) is set to
“1”. After the second-byte address data is stored into the I²C
data shift register (address 002B16), perform an address com-
parison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RWB bit of the I²C address register
(address 002C16) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are re-
ceived after a RESTART condition is detected, with the value of
the I²C address register (address 002C16). For the data trans-
mission format when the 10-bit addressing format is selected,
refer to Figure 36, (3) and (4).
S Slave address R/W A Data A Data A/A P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd bytes
A
Data A
Data A/A P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
Slave address
A _{2nd bytes}
A
Sr
Slave address
1st 7 bits
R/W
A
Data A
Data A P
7 bits
“0”
8 bits
7 bits
“1”
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 36 Address data communication format
: Master to slave
: Slave to master
Rev.1.01 Aug 02, 2004 page 32 of 96