M37517F8HP Datasheet, PDF (93/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
TIMING REQUIREMENTS
Table 31 Timing requirements
(VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tW(RESET)
Reset input “L” pulse width
tC(XIN)
External clock input cycle time
tWH(XIN)
External clock input “H” pulse width
tWL(XIN)
External clock input “L” pulse width
tC(CNTR)
CNTR0, CNTR1 input cycle time
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
tWH(INT)
INT0 to INT3 input “H” pulse width
tWL(INT)
INT0 to INT3 input “L” pulse width
tC(SCLK1)
Serial I/O1 clock input cycle time (Note)
tWH(SCLK1)
Serial I/O1 clock input “H” pulse width (Note)
tWL(SCLK1)
Serial I/O1 clock input “L” pulse width (Note)
tsu(RxD-SCLK1) Serial I/O1 clock input set up time
th(SCLK1-RxD)
Serial I/O1 clock input hold time
tC(SCLK2)
Serial I/O2 clock input cycle time
tWH(SCLK2)
Serial I/O2 clock input “H” pulse width
tWL(SCLK2)
Serial I/O2 clock input “L” pulse width
tsu(SIN2-SCLK2) Serial I/O2 clock input set up time
th(SCLK2-SIN2)
Serial I/O2 clock input hold time
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Min.
20
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Limits
Typ.
Max.
Unit
XIN cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS
Table 32 Switching characteristics
(VCC = 3.0 to 3.6 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ. Max.
Unit
tWH (SCLK1)
Serial I/O1 clock output “H” pulse width
tC(SCLK1)/2–50
ns
tWL (SCLK1)
td (SCLK1-TXD)
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
tC(SCLK1)/2–50
ns
350
ns
tv (SCLK1-TXD) Serial I/O1 output valid time (Note 1)
–30
ns
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Fig. 87
tC(SCLK2)/2–240
tC(SCLK2)/2–240
50
ns
50
ns
ns
ns
td (SCLK2-SOUT2) Serial I/O2 output delay time (Note 2)
400
ns
tv (SCLK2-SOUT2) Serial I/O2 output valid time (Note 2)
0
ns
tf (SCLK2)
Serial I/O2 clock output falling time
50
ns
tr (CMOS)
tf (CMOS)
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
20 50
ns
20 50
ns
Notes 1: For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Rev.1.01 Aug 02, 2004 page 93 of 96