M37517F8HP Datasheet, PDF (58/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
The M37517F8 (flash memory version) has an internal new
DINOR (Divided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 5 V, and 2 power sources
when VPP is 5 V and VCC is 3.3-5.0 V in the CPU rewrite and stan-
dard serial I/O modes.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
The flash memory of the M37517F8 is divided into User ROM area
and Boot ROM area as shown in Figure 64.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
Parallel I/O mode
800016
FFFF16
Block 1 : 32 kbyte
User ROM area
BSEL = 0
F00016
FFFF16
4 kbyte
Boot ROM area
BSEL = 1
CPU rewrite mode, standard serial I/O mode
Product name
M37517F8
Flash memory
start address
800016
800016
Block 1 : 32 kbyte
FFFF16
User ROM area
User area / Boot area selection bit = 0
F00016
FFFF16
4 kbyte
Boot ROM area
User area / Boot area selection bit = 1
Notes 1: The Boot ROM area can be rewritten in only parallel input/
output mode. (Access to any other areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 64 Block diagram of built-in flash memory
Rev.1.01 Aug 02, 2004 page 58 of 96