M37517F8HP Datasheet, PDF (29/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I²C status
register (address 002D16) at the same time after writing the slave
address to the I²C data shift register (address 002B16) with the
condition in which the ES0 bit of the I²C control register (address
002E16) is “1” and the BB flag is “0”, a START condition occurs.
After that, the bit counter becomes “0002” and an SCL for 1 byte is
output. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 30, the START condition generating timing diagram, and
Table 6, the START condition generating timing table.
I²C status register
write signal
SCL
SDA
Setup
time
Hold time
Fig. 30 START condition generating timing diagram
Table 6 START condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0 µs (20 cycles)
5.0 µs (20 cycles)
High-speed clock mode
2.5 µs (10 cycles)
2.5 µs (10 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
STOP Condition Generating Method
When the ES0 bit of the I²C control register (address 002E16) is
“1”, write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I²C status register (address 002D16) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 31, the STOP condition generating timing
diagram, and Table 7, the STOP condition generating timing table.
I²C status register
write signal
SCL
SDA
Setup
time
Hold time
Fig. 31 STOP condition generating timing diagram
Table 7 STOP condition generating timing table
Item
Standard clock mode High-speed clock mode
Setup time
5.0 µs (20 cycles)
3.0 µs (12 cycles)
Hold time
4.5 µs (18 cycles)
2.5 µs (10 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 32, 33, and Table 8. The START/STOP condition is set by
the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 8).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 8, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
SCL
SDA
BB flag
SCL release time
Setup
time
Hold time
BB flag
set
time
Fig. 32 START condition detecting timing diagram
SCL
SDA
BB flag
SCL release time
Setup
time
Hold time
BB flag
reset
time
Fig. 33 STOP condition detecting timing diagram
Table 8 START condition/STOP condition detecting conditions
Standard clock mode
High-speed clock mode
SCL release time SSC value + 1 cycle (6.25 µs) 4 cycles (1.0 µs)
Setup time
SSC value + 1
2
cycle < 4.0 µs (3.125 µs)
2 cycles (1.0 µs)
Hold time
SSC value + 1 _{cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs)}
2
BB flag set/
reset time
SSC value
2
–1
+ 2 cycles (3.375 µs)
3.5 cycles (0.875 µs)
Note: Unit : Cycle number of system clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I²C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
Rev.1.01 Aug 02, 2004 page 29 of 96