M37517F8HP Datasheet, PDF (23/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
MULTI-MASTER I²C-BUS INTERFACE
The multi-master I²C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I²C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 23 shows a block diagram of the multi-master I²C-BUS in-
terface and Table 4 lists the multi-master I²C-BUS interface
functions.
This multi-master I²C-BUS interface consists of the I²C address
register, the I²C data shift register, the I²C clock control register,
the I²C control register, the I²C status register, the I²C start/stop
condition control register and other control circuits.
When using the multi-master I²C-BUS interface, set 1 MHz or
more to φ .
Note: Renesas Technology Corporation assumes no responsibility for in-
fringement of any third-party’s rights or originating in the use of the
connection control function between the I²C-BUS interface and the
ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I²C control regis-
ter (002E16).
Table 4 Multi-master I²C-BUS interface functions
Item
Format
Communication mode
Function
In conformity with Philips I²C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I²C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
SCL clock frequency 16.1 kHz to 400 kHz (at φ = 4 MHz)
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
b7
I²C address register b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
S0D
Interrupt
generating
circuit
Interrupt request signal
(IICIRQ)
Serial data
(SDA)
Noise
elimination
circuit
Data
control
circuit
Address comparator
b7
I²C data shift register
S0
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
S2D
I²C start/stop condition
control register
AL
circuit
b0
b7
b0
AL AAS AD0 LRB
MST TRX BB PIN
S1
I²C status register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
b0
b7
b0
ACK
ACK FAST
BIT ^MODE
CCR4
CCR3
CCR2
CCR1
CCR0
TISS
TSEL
10BIT
SAD
ALS
ES0 BC2 BC1
BC0
S2
I²C clock control register
S1D I²C control register
Clock division
System clock (φ)
Bit counter
Fig. 23 Block diagram of multi-master I²C-BUS interface
✽ : Purchase of Renesas Technology Corporation‘s I²C components conveys a license under the Philips I²C Patent Rights to use these components an I²C
system, provided that the system conforms to the I²C Standard Specification as defined by Philips.
Rev.1.01 Aug 02, 2004 page 23 of 96