M37517F8HP Datasheet, PDF (12/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
Table 3 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
INT0
Priority
1
2
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
Remarks
Non-maskable
External interrupt
(active edge selectable)
SCL, SDA
At detection of either rising or External interrupt
3
FFF916
FFF816
falling edge of SCL or SDA input (active edge selectable)
INT1
INT2
At detection of either rising or External interrupt
4
FFF716
FFF616
falling edge of INT1 input
(active edge selectable)
At detection of either rising or External interrupt
5
FFF516
FFF416
falling edge of INT2 input
(active edge selectable)
INT3
Serial I/O2
I²C
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O1
reception
Serial I/O1
transmission
Over current
detection
CNTR0
CNTR1
6
FFF316
7
FFF116
8
FFEF16
9
FFED16
10
FFEB16
11
FFE916
12
FFE716
13
FFE516
14
FFE316
15
FFE116
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
At detection of either rising or
falling edge of INT3 input
At completion of serial I/O2 data
reception
At completion of data transfer
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At short current is detected, at
over current is detected, or at
wake up current is detected.
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
STP release timer underflow
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
Valid when short current detector
or over current detector, or wake
up current detector is selected.
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
A/D converter
16
Current integration
FFDF16
FFDE16
At completion of A/D conversion
At end of current integration
period, or at end of calibration
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Valid when current integrator is
selected
Non-maskable software interrupt
Rev.1.01 Aug 02, 2004 page 12 of 96