M37517F8HP Datasheet, PDF (30/98 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7517 Group
[I²C START/STOP Condition Control Register
(S2D)] 003016
The I²C START/STOP condition control register (address 003016)
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 9.
Do not set “000002” or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
Refer to Table 9, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
b7
b0
I²C START/STOP condition
SIS SIP ^{SSC4 SSC3 SSC2 SSC1 SSC0} _{control register}
(S2D : address 003016)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
STP/Low speed mode data receive
enable bit
0 : disable
1 : enable
Fig. 34 Structure of I²C START/STOP condition control register
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
•Bit 7: STP/Low speed mode data receive enable bit
Selecting this bit “1” enables I²C to receive the start condition ad-
dress data even if the CPU is stopping or running at the low speed
mode. The detecting the falling edge of the SDA pin, RC on-chip
oscillator begins oscillation, and receive the start condition ad-
dress data. After receiving the last bit of address data ( in case of
ACK clock bit =“1”, after receiving ACK bit), SCL/SDA interrupt
and I²C interrupt are requested at the same time. And then SCL
pin becomes low hold state as a result of becoming SCL pin low
hold bit “0”. During this state, it is possible to start the Xin oscilla-
tion. And after oscillation becomes stable, normal I²C operation
begins. If the start condition which is not satisfied the hold time of
start condition is input, SCL/SDA interrupt is requested.
Note: When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I²C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I²C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
Table 9 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
Main clock
divide ratio
System
clock φ
(MHz)
START/STOP
condition
control register
SCL release time
(µs)
Setup time
(µs)
Hold time
(µs)
XXX11010
6.75 µs (27 cycles)
3.375 µs (13.5 cycles) 3.375 µs (13.5 cycles)
8
2
4
XXX11000
6.25 µs (25 cycles)
3.125 µs (12.5 cycles) 3.125 µs (12.5 cycles)
8
8
1
XXX00100
5.0 µs (5 cycles)
2.5 µs (2.5 cycles)
2.5 µs (2.5 cycles)
XXX01100
6.5 µs (13 cycles)
3.25 µs (6.5 cycles)
3.25 µs (6.5 cycles)
4
2
2
XXX01010
5.5 µs (11 cycles)
2.75 µs (5.5 cycles)
2.75 µs (5.5 cycles)
2
2
1
XXX00100
5.0 µs (5 cycles)
2.5 µs (2.5 cycles)
2.5 µs (2.5 cycles)
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Rev.1.01 Aug 02, 2004 page 30 of 96