H8S2112R Datasheet, PDF (87/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 2 CPU
End of
exception
handling
Program execution
state
SLEEP
instruction
SLEEP
instruction
with
with
LSON = 0 and
SSBY = 0
LSON = 0,
PSS = 0, and
SSBY = 1
Request for
exception
handling
Sleep mode
Exception-handling state
RES = high
Interrupt
request
External interrupt
request
Software standby mode
Power-down state^*2
Reset state^*1
Notes: 1. From any state, a transition to the reset state is made whenever the RES pin
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. The power-down state also includes watch mode. For details, refer to section 26, Power-Down Modes.
Figure 2.11 State Transitions
Rev. 1.00 May 09, 2008 Page 61 of 954
REJ09B0462-0100