H8S2112R Datasheet, PDF (500/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.14 SCIF Control Register (SCIFCR)
SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit Bit Name Initial Value R/W Description
7
SCIFOE1 0
6
SCIFOE0 0
R/W These bits enable or disable PORT output of the
R/W ^SCIF.
For details, see table 16.5.
5

0
R/W Reserved
The initial value should not be modified.
4
OUT2LOOP 0
R/W Enables or disables interrupts during a loopback
test.
0: Interrupt enabled
1: Interrupt disabled
3
CKSEL1
0
2
CKSEL0
0
R/W These bits select the clock (SCLK) to be input to
R/W ^{the baud rate generator.}
00: LCLK divided by 18
01: System clock divided by 11
10: Reserved for LCLK (not selectable)
11: Reserved for system clock (not selectable)
1
SCIFRST 0
R/W Resets the baud rate generator, FRSR, and FTSR.
0: Normal operation
1: Reset
0
REGRST 0
R/W Resets registers (except SCIFCR) accessible from
the H8S CPU or LPC interface.
0: Normal operation
1: Reset
Rev. 1.00 May 09, 2008 Page 474 of 954
REJ09B0462-0100