H8S2112R Datasheet, PDF (465/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 15 CIR Interface
• HHMAX
Initial
Bit
Bit Name
Value R/W Description
15
FLT1
0
R/W Number of Stages of Noise Canceler Circuit Select
14
FLT0
0
R/W 00: The noise canceler circuit consists of one stage
01: The noise canceler circuit consists of two stages
10: The noise canceler circuit consists of three
stages
11: The noise canceler circuit consists of four stages
13
FLTE
0
R/W Noise Canceler Circuit Enable
0: Disables the noise canceler circuit
1: Enables the noise canceler circuit
12
FLTCK1
0
11
FLTCK0
0
R/W Division Ratio Select for Noise Canceler Circuit
R/W ^Clock
Divides the frequency of the sampling clock for CIR
reception selected by BRR.
00: Not divided
01: Divided by 2
10: Divided by 4
11: Divided by 8
10

0
R/W Reserved
The initial value should not be changed.
9 to 0 HHMAX9 to All 0
HHMAX0
R/W Specifies the maximum high-level period for a
header or repeat header and the maximum low-level
period for a stop.
Rev. 1.00 May 09, 2008 Page 439 of 954
REJ09B0462-0100