H8S2112R Datasheet, PDF (238/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 9 8-Bit PWM Timer (PWMU)
9.3.8 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5)
PWMREG are 8-bit readable/writable registers used to set the high period (duty) of the PWM
output pulse. The initial value is H'00.
(1) 8-Bit Single Pulse Mode
Directly set the high period of the pulse for PWM output. With PWMREG registers, the duty
cycle of the PWM output pulse is specified as a value from 0/255 to 255/255 with a resolution of
1/255.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
Output pulse high period = (PWM cycle × m) / 255 (0 ≤ m ≤ 255)
(2) 12-Bit Single Pulse Mode
Directly set the high period of the pulse for PWM output. With PWMREG registers, the duty
cycle of the PWM output pulse is specified as a value from 0/4095 to 4095/4095 with a resolution
of 1/4095.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
Output pulse high period = (PWM cycle × m) / 4095 (0 ≤ m ≤ 4095)
Set the respective high-level pulse periods by using the following register combinations:
PWMREG1 (higher order) and PWMREG0 (lower order), PWMREG3 (higher order) and
PWMREG2 (lower order), and PWMREG5 (higher order) and PWMREG4 (lower order).
Note:
Setting of the bits 3 to 0 in the higher order registers and lower order registers is enabled.
The bits 7 to 4 in the higher order registers are disabled. The higher order registers must be
set after setting the lower order registers, otherwise the output performance is not as
desired.
Rev. 1.00 May 09, 2008 Page 212 of 954
REJ09B0462-0100