H8S2112R Datasheet, PDF (136/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 6 Interrupt Controller
• ISR
Bit Bit Name Initial Value R/W Description
7
IRQ7F
0
R/(W)* [Setting condition]
6
IRQ6F
0
5
IRQ5F
0
4
IRQ4F
0
3
IRQ3F
0
2
IRQ2F
0
1
IRQ1F
0
0
IRQ0F
0
R/(W)* When the interrupt source selected by the ISCR
R/(W)* ^{registers occurs}
R/(W)* ^{[Clearing conditions]}
R/(W)* ^•
R/(W)*
R/(W)* ^•
R/(W)*
When writing 0 to IRQnF flag after reading
IRQnF = 1
When interrupt exception handling is executed
when low-level detection is set and IRQn or
ExIRQn input is high
• When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
(n = 7 to 0)
Note: The IRQn or ExIRQn pin is selected by the
IRQ sense port select register (ISSR). The
ExIRQ5 to ExIRQ0 pins are not supported.
Note: * Only 0 can be written for clearing the flag.
Rev. 1.00 May 09, 2008 Page 110 of 954
REJ09B0462-0100