H8S2112R Datasheet, PDF (349/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 12 8-Bit Timer (TMR)
Table 12.3 Clock Input to TCNT and Count Condition (1)
Channel CKS2
TMR_0 0
0
0
0
0
0
0
1
TMR_1 0
0
0
0
0
0
0
1
TCR
CKS1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
CKS0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
STCR
ICKS1 ICKS0
—
—
—
0
—
1
—
0
—
1
—
0
—
1
—
—
—
—
0
—
1
—
0
—
1
—
0
—
1
—
—
—
Description
Disables clock input
Increments at falling edge of internal
clock φ/8
Increments at falling edge of internal
clock φ/2
Increments at falling edge of internal
clock φ/64
Increments at falling edge of internal
clock φ/32
Increments at falling edge of internal
clock φ/1024
Increments at falling edge of internal
clock φ/256
Increments at overflow signal from
TCNT_1*
Disables clock input
Increments at falling edge of internal
clock φ/8
Increments at falling edge of internal
clock φ/2
Increments at falling edge of internal
clock φ/64
Increments at falling edge of internal
clock φ/128
Increments at falling edge of internal
clock φ/1024
Increments at falling edge of internal
clock φ/2048
Increments at compare-match A from
TCNT_0*
Rev. 1.00 May 09, 2008 Page 323 of 954
REJ09B0462-0100