H8S2112R Datasheet, PDF (827/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 25 Clock Pulse Generator
Section 25 Clock Pulse Generator
This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock,
bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty
correction circuit, system clock select circuit, subclock input circuit, and subclock waveform
forming circuit. Figure 25.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
EXCL
(ExEXCL)
Subclock
input circuit
Duty
φ
correction
circuit
Subclock
waveform
forming circuit
φSUB
System
clock
select _φ
circuit
Bus master
clock to CPU
WDT_1
count clock,
CIR
sampling clock
System clock
to φ pin
Internal clock
to on-chip
peripheral modules
Figure 25.1 Block Diagram of Clock Pulse Generator
The subclock input is controlled by software according to the EXCLE bit and the EXCLS bit in
the port control register (PTCNT0) settings in the low power control register (LPWRCR). For
details on LPWRCR, see section 26.1.2, Low-Power Control Register (LPWRCR). For details on
PTCNT0, see section 8.3.1, Port Control Register 0 (PTCNT0).
Rev. 1.00 May 09, 2008 Page 801 of 954
REJ09B0462-0100