H8S2112R Datasheet, PDF (123/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 6 Interrupt Controller
Section 6 Interrupt Controller
6.1 Features
• Two interrupt control modes
Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system
control register (SYSCR).
• Priorities settable with ICR
An interrupt control register (ICR) is provided for setting in each module interrupt priority
levels for all interrupt requests excluding NMI and address breaks.
• Three-level interrupt mask control
By means of the interrupt control mode, I and UI bits in CCR and ICR, 3-level interrupt mask
control is performed.
• Forty-nine external interrupt pins
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be independently selected for IRQ15 to IRQ0. Either of falling-edge or rising-
edge detection can be independently selected for WUE15 to WUE0. When the EIVS bit in the
system control register 3 (SYSCR3) is cleared to 0, the IRQ6 interrupt is generated by IRQ6 or
KIN7 to KIN0. The IRQ7 interrupt is generated by IRQ7 or KIN15 to KIN8. When the EIVS
bit is set to 1, interrupts are requested on the falling edge of KIN15 to KIN0.
• Two interrupt vector addresses are selectable
H8S/2140B Group compatible interrupt vector addresses or extended interrupt vector
addresses are selected depending on the EIVS bit in system control register 3 (SYSCR3). In
extended mode, independent vector addresses are assigned for the interrupt vector addresses of
KIN7 to KIN0 or KIN15 to KIN8 interrupts.
• General ports for IRQ15 to IRQ6 and ExIRQ15 to ExIRQ06 input are selectable
Rev. 1.00 May 09, 2008 Page 97 of 954
REJ09B0462-0100