H8S2112R Datasheet, PDF (694/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 21 FSI Interface
• FSIARL
R/W
Initial
Bit Bit Name Value EC Host Description
7 to 0 bit 7 to bit 0 All 0 R
 These bits store bits [7:0] of the SPI flash memory
address.
21.3.19 FSI Write Data Registers HH, HL, LH, and LL (FSIWDRHH, FSIWDRHL,
FSIWDRLH, and FSIWDRLL)
FSIWDR stores data to be written to the SPI flash memory. If the host address matches FSIHBAR
during LPC/FW memory write cycle, the FSIWDR value will be updated. FSIHBAR value is not
updated by command access.
• FSIWDRHH
Initial
Bit Bit Name Value
7 to 0 bit 31 to All 0
bit 24
R/W
EC Host Description
R  These bits store bits [31:24] of the SPI flash memory
write data
• FSIWDRHL
Initial
Bit Bit Name Value
7 to 0 bit 23 to All 0
bit 16
R/W
EC Host Description
R  These bits store bits [23:16] of the SPI flash memory
write data.
Rev. 1.00 May 09, 2008 Page 668 of 954
REJ09B0462-0100