H8S2112R Datasheet, PDF (484/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3 Register Descriptions
The SCIF has the following registers. The register configuration of the SCIF is shown below.
Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details,
see table 16.3. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and serial IRQ
control register 4 (SIRQCR4), see section 20, LPC Interface (LPC).
Table 16.2 Register Configuration
Register Name
Abbreviation R/W
Host interface control register 5 HICR5
R/W
Module stop control register B MSTPCRB R/W
Receive buffer register
FRBR
R
Transmitter holding register
FTHR
W
Divisor latch L
FDLL
R/W
Interrupt enable register
FIER
R/W
Divisor latch H
FDLH
R/W
Interrupt identification register FIIR
R
FIFO control register
FFCR
W
Line control register
FLCR
R/W
Modem control register
FMCR
R/W
Line status register
FLSR
R
Modem status register
FMSR
R
Scratch pad register
FSCR
R/W
SCIF control register
SCIFCR
R/W
SCIF address register H
SCIFADRH R/W
SCIF address register L
SCIFADRL R/W
Serial IRQ control register 4
SIRQCR4
R/W
Initial Value Address
H'00
H'FFFE33
H'00
H'FFFE7F
H'00
H'FFFC20

H'00
H'00
H'FFFC21
H'00
H'01
H'FFFC22
H'00
H'00
H'FFFC23
H'00
H'FFFC24
H'60
H'FFFC25

H'FFFC26
H'00
H'FFFC27
H'00
H'FFFC28
H'03
H'FFFDC4
H'F8
H'FFFDC5
H'00
H'FFFE3B
Data
Bus
Width
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Rev. 1.00 May 09, 2008 Page 458 of 954
REJ09B0462-0100