H8S2112R Datasheet, PDF (19/984 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

16.3.2 Receive Buffer Register (FRBR) .......................................................................... 459
16.3.3 Transmitter Shift Register (FTSR)........................................................................ 460
16.3.4 Transmitter Holding Register (FTHR).................................................................. 460
16.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 460
16.3.6 Interrupt Enable Register (FIER).......................................................................... 461
16.3.7 Interrupt Identification Register (FIIR)................................................................. 462
16.3.8 FIFO Control Register (FFCR)............................................................................. 464
16.3.9 Line Control Register (FLCR) .............................................................................. 465
16.3.10 Modem Control Register (FMCR)........................................................................ 466
16.3.11 Line Status Register (FLSR)................................................................................. 468
16.3.12 Modem Status Register (FMSR)........................................................................... 472
16.3.13 Scratch Pad Register (FSCR)................................................................................ 473
16.3.14 SCIF Control Register (SCIFCR) ......................................................................... 474
16.4 Operation ........................................................................................................................... 476
16.4.1 Baud Rate ............................................................................................................. 476
16.4.2 Operation in Asynchronous Communication........................................................ 477
16.4.3 Initialization of the SCIF ...................................................................................... 478
16.4.4 Data Transmission/Reception with Flow Control................................................. 481
16.4.5 Data Transmission/Reception Through the LPC Interface ................................... 487
16.5 Interrupt Sources................................................................................................................ 490
16.6 Usage Note......................................................................................................................... 490
16.6.1 Power-Down Mode When LCLK is Selected for SCLK ...................................... 490
Section 17 I²C Bus Interface (IIC) .....................................................................491
17.1 Features.............................................................................................................................. 491
17.2 Input/Output Pins............................................................................................................... 494
17.3 Register Descriptions ......................................................................................................... 495
17.3.1 I²C Bus Data Register (ICDR) .............................................................................. 496
17.3.2 Slave Address Register (SAR).............................................................................. 497
17.3.3 Second Slave Address Register (SARX) .............................................................. 498
17.3.4 I²C Bus Mode Register (ICMR)............................................................................ 500
17.3.5 I²C Bus Control Register (ICCR).......................................................................... 503
17.3.6 I²C Bus Status Register (ICSR)............................................................................. 512
17.3.7 I²C Bus Control Initialization Register (ICRES)................................................... 516
17.3.8 I²C Bus Extended Control Register (ICXR).......................................................... 517
17.4 Operation ........................................................................................................................... 521
17.4.1 I²C Bus Data Format ............................................................................................. 521
17.4.2 Initialization.......................................................................................................... 523
17.4.3 Master Transmit Operation................................................................................... 523
17.4.4 Master Receive Operation .................................................................................... 528
Rev. 1.00 May 09, 2008 Page xix of xxvi