RX23T Datasheet, PDF (86/98 Pages) Renesas Technology Corp – 40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS

RX23T Group
5. Electrical Characteristics
5.9 ROM (Flash Memory for Code Storage) Characteristics
Table 5.37 ROM (Flash Memory for Code Storage) Characteristics (1)
Item
Reprogramming/erasure cycle*¹
Data hold time
After 1000 times of N_PEC
Symbol
N_PEC
t_DRP
Min.
1000
20*^2, *³
Typ.
Max.
Unit
Conditions
—
—
Times
—
—
Year T_a = +85°C
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided from Renesas Electronics.
Note 3. This result is obtained from reliability testing.
Table 5.38 ROM (Flash Memory for Code Storage) Characteristics (2): High-Speed Operating Mode
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VREFH0 = VCC to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T_a = –40 to +105°C
Temperature range for the programming/erasure operation: T_a = –40 to +85°C
Item
Programming time
Erasure time
8-byte
2-Kbyte
128-Kbyte
(when block
erase
command
used)
Symbol
t_P8
t_E2K
FCLK = 1 MHz
Min.
Typ.
Max.
—
112.0
967.0
—
8.7
278.1
—
239.7
5111.4
FCLK = 32 MHz
Unit
Min.
Typ.
Max.
—
52.3
490.5
μs
—
5.5
214.6
ms
—
25.9
734.3
ms
128-Kbyte
t_E128K
—
234.5 4906.8
—
(when all-
block erase
command
used)
Blank check time
8-byte
2-Kbyte
Erase operation forcible stop time
Start-up area switching setting time
Access window time
ROM mode transition wait time 1
ROM mode transition wait time 2
t_BC8
—
—
55.0
—
t_BC2K
—
—
1840.0
—
t_SED
—
—
18.0
—
t_SAS
—
12.3
566.5
—
t_AWS
—
12.3
566.5
—
t_DIS
2.0
—
—
2.0
t_MS
5.0
—
—
5.0
20.6
524.6
ms
—
16.1
μs
—
135.7
μs
—
10.7
μs
6.2
433.5
ms
6.2
433.5
ms
—
—
μs
—
—
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing of the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK should be ±3.5%.
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
Page 86 of 98