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RX23T Datasheet, PDF (3/98 Pages) Renesas Technology Corp – 40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS | |||
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RX23T Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Classification
Interrupt
Module/Function
Interrupt controller (ICUb)
DMA
I/O ports
Data transfer controller
(DTCa)
General I/O ports
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 3 (MTU3c)
Port output enable 3
(POE3b)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
8-bit timer (TMR)
Description
ï· Interrupt vectors: 83
ï· External interrupts: 7 (NMI, IRQ0 to IRQ5 pins)
ï· Non-maskable interrupts: 5 (NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
ï· 16 levels specifiable for the order of priority
ï· Transfer modes: Normal transfer, repeat transfer, and block transfer
ï· Activation sources: Interrupts
ï· Chain transfer function
64-/52-/48-pin
ï· I/O: 50/40/37
ï· Input: 1/1/1
ï· Pull-up resistors: 50/40/37
ï· Open-drain outputs: 42/32/29
ï· 5-V tolerance: 2/2/2
Capable of selecting the input/output function from multiple pins
ï· 6 units (16bis à 6 channels)
ï· Provides up to 16 pulse-input/output lines and three pulse-input lines
ï· Select from among fourteen counter-input clock signals for each channel (PCLK/1, PCLK/2, PCLK/4,
PCLK/8, PCLK/16, PCLK/32, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC,
MTCLKD, MTIOC1A) other than channel 1/3/4, for which only eleven signals are available, channel 2
for 12, channel 5 for 10
ï· 26 output compare/input capture registers
ï· Counter clear operation (with compare match- or input capture-sourced simultaneous counter clear
capability)
ï· Simultaneous writing to multiple timer counters (TCNT)
ï· Simultaneous register input/output by synchronous counter operation
ï· Buffer operation
ï· Cascaded operation
ï· 28 interrupt sources
ï· Automatic transfer of register data
ï· Pulse output modes: Toggle/PWM/complementary PWM/reset-synchronized PWM
ï· Complementary PWM output mode
3-phase non-overlapping waveform output for inverter control
Automatic dead time setting
Adjustable PWM duty cycle: from 0 to 100%
A/D conversion request delaying function
Interrupt at crest/trough can be skipped
Double buffer function
ï· Reset-synchronized PWM mode
Outputs three phases each for positive and negative PWM waveforms in user-specified duty cycle
ï· Phase counting modes: 16-bit mode (channel 1 and 2)/32-bit mode (channel 1 and 2)
ï· Dead time compensation counter function
ï· A/D converter start trigger can be generated
ï· A/D converter start triggers can be skipped
ï· Signals from the input capture and external counter clock pins are input via a digital filter
Controls the high-impedance state of the MTUâs waveform output pins
ï· (16 bits à 2 channels) à 2 units
ï· Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
ï· 14 bits à 1 channel
ï· Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
ï· (8 bits à 2 channels) à 2 units
ï· Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
ï· Pulse output and PWM output with any duty cycle are available
ï· Two channels can be cascaded and used as a 16-bit timer
ï· Generates A/D conversion start trigger
ï· Generates baud rate clock for the SCI5
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
Page 3 of 98
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