RX23T Datasheet, PDF (82/98 Pages) Renesas Technology Corp – 40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS

RX23T Group
5. Electrical Characteristics
Table 5.35 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VREFH0 = VCC to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item
Wait time after power-on reset cancellation
Wait time after voltage monitoring 0 reset
cancellation
Wait time after voltage monitoring 1 reset
cancellation
Wait time after voltage monitoring 2 reset
cancellation
Response delay time
Minimum VCC down time*¹
Power-on reset enable time
LVD operation stabilization time (after LVD is
enabled)
Hysteresis width (LVD1 and LVD2)
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
t_POR
t_LVD0
―
28.4
―
―
568
―
ms Figure 5.51
μs Figure 5.52
t_LVD1
―
100
―
μs Figure 5.53
t_LVD2
―
100
―
μs Figure 5.54
t_det
―
―
350
μs Figure 5.50
t_VOFF
350
―
―
μs Figure 5.50, VCC = 1.0 V or
above
t_W(POR)
1
―
―
ms Figure 5.51, VCC = below 1.0
V
Td_(E-A)
―
―
300
μs Figure 5.53, Figure 5.54
V_LVH
―
70
―
mV Vdet1_0 to 4 selected
―
60
―
Vdet1_5 to 8, LVD2 selected
Note:
Note 1.
These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det1,
and V_det2 for the POR/LVD.
VCC
V_POR
1.0 V
Internal reset signal
(active-low)
Figure 5.50 Voltage Detection Reset Timing
t_VOFF
t_det t_det t_POR
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
Page 82 of 98