RX23T Datasheet, PDF (65/98 Pages) Renesas Technology Corp – 40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS

RX23T Group
5. Electrical Characteristics
5.3.5
Timing of On-Chip Peripheral Modules
Table 5.23 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VREFH0 = VCC to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit
*1
Test
Conditions
I/O ports
MTU3
Input data pulse width
Input capture input pulse width
t_PRW
1.5
— t_Pcyc Figure 5.34
Single-edge setting
t_TICW
3
— t_PAcyc Figure 5.35
Both-edge setting
5
—
Timer clock pulse width
Single-edge setting
t_TCKWH,
3
Both-edge setting
t_TCKWL
5
— t_PAcyc Figure 5.36
—
Phase counting mode
5
—
POE3
TMR
POE# input pulse width
Timer clock pulse width
t_POEW
1.5
Single-edge setting
t_TMCWH,
1.5
Both-edge setting
t_TMCWL
2.5
— t_Pcyc Figure 5.37
— t_Pcyc Figure 5.38
—
SCI
Input clock cycle
Asynchronous
Clock synchronous
t_Scyc
4
— t_Pcyc Figure 5.39
6
—
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
Asynchronous
t_Scyc
16
— t_Pcyc Figure 5.40
Clock synchronous
4
—
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time Clock synchronous
(master)
t_SCKW
0.4
0.6 t_Scyc
t_SCKr
—
20 ns
t_SCKf
—
20 ns
t_TXD
—
40 ns
Transmit data delay time Clock
VCC = 4.0 V or above
(slave)
synchronous _{VCC = 2.7 V or above}
Receive data setup time Clock
VCC = 4.0 V or above
t_RXS
(master)
synchronous _{VCC = 2.7 V or above}
—
40 ns
—
65 ns
40
— ns
65
— ns
Receive data setup time Clock synchronous
(slave)
Receive data hold time Clock synchronous
A/D converter Trigger input pulse width
CAC
CACREF input pulse width
t_Pcyc ≤ t_cac*2
t_Pcyc > t_cac*2
40
— ns
t_RXH
40
— ns
t_TRGW
1.5
— t_Pcyc Figure 5.41
t_CACREF 4.5 t_cac + 3 t_Pcyc —
ns
5 t_cac + 6.5 t_Pcyc
Note 1. t_Pcyc: PCLK cycle, t_PAcyc: PCLKA cycle
Note 2. t_cac: CAC count clock source cycle
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
Page 65 of 98