RX23T Datasheet, PDF (66/98 Pages) Renesas Technology Corp – 40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS

RX23T Group
5. Electrical Characteristics
Table 5.24 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VREFH0 = VCC to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, T_a = –40 to +105°C,
C = 30pF
Item
RSPI RSPCK clock
cycle
Master
Slave
RSPCK clock Master VCC = 4.0 V or above
high pulse width
VCC = 2.7 V or above
Slave
RSPCK clock Master VCC = 4.0 V or above
low pulse width
VCC = 2.7 V or above
Slave
RSPCK clock
rise/fall time
Output VCC = 4.0 V or above
VCC = 2.7 V or above
Input
Symbol
Min.
t_SPcyc
2
8
t_SPCKWH
t_SPCKWL
t_SPCKr,
t_SPCKf
(t_SPcyc – t_SPCKr –
t_SPCKf)/2 – 5
(t_SPcyc – t_SPCKr –
t_SPCKf)/2 – 8
(t_SPcyc – t_SPCKr –
t_SPCKf)/2
(t_SPcyc – t_SPCKr –
t_SPCKf)/2 – 5
(t_SPcyc – t_SPCKr–
t_SPCKf)/2 – 8
(t_SPcyc – t_SPCKr –
t_SPCKf)/2
—
—
—
Max.
4096
4096
—
—
—
—
—
—
6
10
0.1
Unit
Test
Conditions
t_Pcyc*¹ Figure 5.42
ns
ns
ns
μs/V
Data input setup Master VCC = 4.0 V or above
t_SU
10
—
time
VCC = 2.7 V or above
26
—
Slave
25 – t_Pcyc
—
Data input hold Master RSPCK set to a division ratio
t_H
t_Pcyc
—
time
other than PCLKB divided by 2
RSPCK set to PCLKB divided t_HF
0
—
by 2
Slave
SSL setup time Master
Slave
t_H
20 + 2 × t_Pcyc
—
t_LEAD –30 + N*² × t_SPcyc
—
2
—
SSL hold time Master
Slave
t_LAG –30 + N*³ × t_SPcyc
—
2
—
Data output
Master VCC = 4.0 V or above
t_OD
—
10
delay time
VCC = 2.7 V or above
—
14
ns Figure 5.43
to
Figure 5.46
ns
ns
t_Pcyc
ns
t_Pcyc
ns
Slave
Data output hold Master 2.7 V or above
time
Slave
Successive
transmission
delay time
Master
Slave
MOSI and MISO Output
rise/fall time
Input
SSL rise/fall
time
Output
Input
Slave access time
Slave output release time
t_OH
t_TD
t_Dr, t_Df
t_SSLr,
t_SSLf
t_SA
t_REL
—
3 × t_Pcyc + 65
0
—
0
—
t_SPcyc + 2 × t_Pcyc
4 × t_Pcyc
—
8 × t_SPcyc + 2 ×
t_Pcyc
—
10
—
1
—
10
—
1
—
6
—
5
ns
ns
ns
μs
ns
μs
t_Pcyc Figure 5.45,
t_Pcyc ^{Figure 5.46}
Note 1. t_Pcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0248EJ0110 Rev.1.10
Jan 13, 2016
Page 66 of 98