HD404639R Datasheet, PDF (86/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

HD404639R Series
Operating States: Serial interface 1 has the following operating states; transitions between them are shown
in figure 67.
• STS wait state (serial interface 2 is in SM2A read wait state)
• Transmit clock wait state
• Transfer state
• Continuous clock output state (only in internal clock mode)
System reset 00
STS instruction wait state
(with octal counter = 000,
transmit clock disabled)
SM1A write 04
Transmit clock wait state
(octal counter = 000)
STS instruction^* 01
Transmit clock 02
Eight transmit clock cycles 03
STS instruction^* ₀₅
(IFS1 ← 1)
External Clock Mode
SM1A write 06
(IFS1 ← 1)
Transfer state
(octal counter ≠ 000)
System reset 10
SM1A write 18
Transmit clock
continuous output state
(PMRA 0, 1 = 00)
SM1A write 14
Transmit clock 17
Transmit clock wait state
(octal counter = 000)
STS instruction wait state
(with octal counter = 000,
transmit clock disabled)
STS instruction* 11
Eight transmit clock cycles 13
STS instruction 16
(IFS1 ← 1)
Transmit clock 12
STS instruction * ₁₅
(IFS1 ← 1)
Transfer state
(octal counter ≠ 000)
Internal Clock Mode
Note: * For serial interface 2, this is accomplished by reading the SM2A register.
Circled numbers are referred to in the text.
Figure 67 Serial Interface State Transition Diagram
The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of
serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1.
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
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