HD404639R Datasheet, PDF (19/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

HD404639R Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt
Priority
RESET, STOPC*
—
INT₀
1
INT₁
2
Timer A
3
Timer B, INT₂
4
Timer C, INT₃
5
Timer D, INT₄
6
Serial 1 and 2
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Note: * The STOPC interrupt request is valid only in stop mode
Vector Address
$0000
$0002
$0004
$0006
$0008
$000A
$000C
$000E
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt Control Bit
INT₀ INT₁ Timer A Timer B Timer C or Timer D or Serial 1 or
or INT₂ INT₃
INT₄
Serial 2
IE
111
1
1
1
1
IF0 ^. IM0
100
0
0
0
0
IF1 ^. IM1
*
1
0
0
0
0
0
IFTA ^. IMTA
*
*
1
0
0
0
0
IFTB ^. IMTB + IF2 ^. IM2
*
*
*
1
0
0
0
IFTC ^. IMTC + IF3 ^. IM3
*
*
*
*
1
0
0
IFTD ^. IMTD + IF4 ^. IM4
*
*
*
*
*
1
0
IFS1 ^. IMS1 + IFS2 ^. IMS2
*
*
*
*
*
*
1
Note: * Can be either 0 or 1. Their values have no effect on operation.
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