HD404639R Datasheet, PDF (101/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

TONER
VT _ref
TONEC
Sine wave
counter D/A
Feedback
Transforma-
tion program
divider
TONER output control
Sine wave
counter D/A
Feedback
Transforma-
tion program
divider
HD404639R Series
2
Tone generator
mode register
(TGM)
Tone generator
2
control register
(TGC)
TONEC output control
f _OSC
400 kHz
800 kHz
1/2
2 MHz
1/5
3.58 MHz
1/9^*3
4 MHz
1/10
7.16 MHz^*2
1/18^*3
8 MHz^*2
1/20
400 kHz ^*3
Selector
2
System clock
selection register 1
(SSR1)
System clock
selection register 2
(SSR2) ^*1
1
Notes: 1. System clock selection register 2 (SSR2) is used to specify the divide-by-9 or divide-by-18 operation
when a 3.58-MHz or 7.16 MHz system clock oscillator is used.
2. Applies to HD40A4638R, HD40A4639R and HD407A4639R.
3. This is 397.8 kHz when f_OSC is 3.58 MHz and 7.16 MHz.
Figure 82 Block Diagram of DTMF Generator Circuit
99